Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA

B. S. Chandrasekhar, S. Deepanjali, Sk. Noor Mahammad. Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA. In IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022. pages 31-35, IEEE, 2022. [doi]

Abstract

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