Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm. JNW, 6(1):36-45, 2011. [doi]
@article{ChandrasettyA11,
title = {FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm},
author = {Vikram Arkalgud Chandrasetty and Syed Mahfuzul Aziz},
year = {2011},
doi = {10.4304/jnw.6.1.36-45},
url = {http://dx.doi.org/10.4304/jnw.6.1.36-45},
researchr = {https://researchr.org/publication/ChandrasettyA11},
cites = {0},
citedby = {0},
journal = {JNW},
volume = {6},
number = {1},
pages = {36-45},
}