Vikram Arkalgud Chandrasetty - researchr alias

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Viewing Publication 1 - 8 from 8

2016

Repeat-accumulate codes for reconciliation in continuous variable quantum key distributionSarah J. Johnson, Vikram Arkalgud Chandrasetty, Andrew M. Lance. ausctw 2016: 18-23 [doi]

2015

Resource efficient LDPC decoders for multimedia communicationVikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. integration, 48:213-220, 2015. [doi]

2014

Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codesVikram Arkalgud Chandrasetty, Sarah J. Johnson, Gottfried Lechner. iet-com, 8(17):3179-3188, 2014. [doi]

2012

A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered PermutationVikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. jnw, 7(3):441-449, 2012. [doi]

An area efficient LDPC decoder using a reduced complexity min-sum algorithmVikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. integration, 45(2):141-148, 2012. [doi]

2011

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing AlgorithmVikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. jnw, 6(1):36-45, 2011. [doi]

A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decodersVikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. icmcs 2011: 1-7 [doi]

VLSI Design - A Practical Guide for FPGA and ASIC ImplementationsVikram Arkalgud Chandrasetty. Springer Briefs in Electrical and Computer Engineering, Springer, 2011. [doi]

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