A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration - researchr publication

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Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu. A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. on Circuits and Systems, 65-II(3):281-285, 2018. [doi]

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