Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo. A Temporal Assertion Extension to Verilog. In Farn Wang, editor, Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings. Volume 3299 of Lecture Notes in Computer Science, pages 499-504, Springer, 2004. [doi]
Abstract is missing.