Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei 0004, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra. Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. In Formal Methods in Computer Aided Design, FMCAD 2021, New Haven, CT, USA, October 19-22, 2021. pages 42-52, IEEE, 2021. [doi]

@inproceedings{ChattopadhyayLP21,
  title = {Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition},
  author = {Saranyu Chattopadhyay and Florian Lonsing and Luca Piccolboni and Deepraj Soni and Peng Wei 0004 and Xiaofan Zhang and Yuan Zhou and Luca P. Carloni and Deming Chen and Jason Cong and Ramesh Karri and Zhiru Zhang and Caroline Trippel and Clark W. Barrett and Subhasish Mitra},
  year = {2021},
  doi = {10.34727/2021/isbn.978-3-85448-046-4_12},
  url = {https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_12},
  researchr = {https://researchr.org/publication/ChattopadhyayLP21},
  cites = {0},
  citedby = {0},
  pages = {42-52},
  booktitle = {Formal Methods in Computer Aided Design, FMCAD 2021, New Haven, CT, USA, October 19-22, 2021},
  publisher = {IEEE},
  isbn = {978-3-85448-046-4},
}