Sudipta Chattopadhyay, Abhik Roychoudhury, Tulika Mitra. Modeling shared cache and bus in multi-cores for timing analysis. In Ed F. Deprettere, Todor Stefanov, editors, 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES '10, St. Goar, Germany, June 29-30, 2010. pages 6, ACM, 2010. [doi]
Abstract is missing.