Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei. A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs. IEEE Trans. on Circuits and Systems, 65-II(11):1519-1523, 2018. [doi]
@article{ChegeniHK18,
title = {A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs},
author = {Amin Chegeni and Khayrollah Hadidi and Abdollah Khoei},
year = {2018},
doi = {10.1109/TCSII.2017.2754639},
url = {https://doi.org/10.1109/TCSII.2017.2754639},
researchr = {https://researchr.org/publication/ChegeniHK18},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {65-II},
number = {11},
pages = {1519-1523},
}