Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Pao-Lung Chen. Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 2554-2557, IEEE, 2008. [doi]

This author has not been identified. Look up 'Pao-Lung Chen' in Google

runs on WebDSL