Gregory K. Chen, Mark Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Y. Borkar. A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. J. Solid-State Circuits, 50(1):59-67, 2015. [doi]
@article{ChenAKSMHAKDB15,
title = {A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS},
author = {Gregory K. Chen and Mark Anders and Himanshu Kaul and Sudhir Satpathy and Sanu K. Mathew and Steven Hsu and Amit Agarwal and Ram Krishnamurthy and Vivek De and Shekhar Y. Borkar},
year = {2015},
doi = {10.1109/JSSC.2014.2369508},
url = {http://dx.doi.org/10.1109/JSSC.2014.2369508},
researchr = {https://researchr.org/publication/ChenAKSMHAKDB15},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {50},
number = {1},
pages = {59-67},
}