Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao. A bit-level pipelined VLSI architecture for the running order algorithm. IEEE Transactions on Signal Processing, 45(8):2140-2144, 1997. [doi]
@article{ChenCH97-0,
title = {A bit-level pipelined VLSI architecture for the running order algorithm},
author = {Chun-Te Chen and Liang-Gee Chen and Jue-Hsuan Hsiao},
year = {1997},
doi = {10.1109/78.611236},
url = {http://dx.doi.org/10.1109/78.611236},
researchr = {https://researchr.org/publication/ChenCH97-0},
cites = {0},
citedby = {0},
journal = {IEEE Transactions on Signal Processing},
volume = {45},
number = {8},
pages = {2140-2144},
}