C.-A. Chen, S. K. Gupta. Efficient BIST TPG design and test set compaction for delay testing via input reduction. In ICCD. pages 32-39, 1998. [doi]
@inproceedings{ChenG98-1,
title = {Efficient BIST TPG design and test set compaction for delay testing via input reduction},
author = {C.-A. Chen and S. K. Gupta},
year = {1998},
doi = {10.1109/ICCD.1998.727020},
url = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727020},
researchr = {https://researchr.org/publication/ChenG98-1},
cites = {0},
citedby = {0},
pages = {32-39},
booktitle = {ICCD},
}