Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs

Chien-Ting Chen, Yoshi Shih-Chieh Huang, Yuan-Ying Chang, Chiao-Yun Tu, Chung-Ta King, Tai-Yuan Wang, Janche Sang, Ming-Hua Li. Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs. In Ching-Hsien Hsu, Xuanhua Shi, Valentina Salapura, editors, Network and Parallel Computing - 11th IFIP WG 10.3 International Conference, NPC 2014, Ilan, Taiwan, September 18-20, 2014. Proceedings. Volume 8707 of Lecture Notes in Computer Science, pages 169-180, Springer, 2014. [doi]

Abstract

Abstract is missing.