Tse-Wei Chen, Makoto Ikeda. Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing. In Hiroaki Kobayashi, Makoto Ikeda, Fumio Arakawa, editors, 2012 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XV, Yokohama, Japan, April 18-20, 2012. pages 1-3, IEEE, 2012. [doi]
@inproceedings{ChenI12,
title = {Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing},
author = {Tse-Wei Chen and Makoto Ikeda},
year = {2012},
doi = {10.1109/COOLChips.2012.6216580},
url = {http://dx.doi.org/10.1109/COOLChips.2012.6216580},
researchr = {https://researchr.org/publication/ChenI12},
cites = {0},
citedby = {0},
pages = {1-3},
booktitle = {2012 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XV, Yokohama, Japan, April 18-20, 2012},
editor = {Hiroaki Kobayashi and Makoto Ikeda and Fumio Arakawa},
publisher = {IEEE},
isbn = {978-1-4673-1201-1},
}