Tse-Wei Chen, Makoto Ikeda. Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing. In Hiroaki Kobayashi, Makoto Ikeda, Fumio Arakawa, editors, 2012 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XV, Yokohama, Japan, April 18-20, 2012. pages 1-3, IEEE, 2012. [doi]
Abstract is missing.