A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS

Qian Chen, Yuan Liang, Chirn Chye Boon. A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020. pages 1-5, IEEE, 2020. [doi]

@inproceedings{ChenLB20-1,
  title = {A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS},
  author = {Qian Chen and Yuan Liang and Chirn Chye Boon},
  year = {2020},
  doi = {10.1109/ISCAS45731.2020.9180949},
  url = {https://doi.org/10.1109/ISCAS45731.2020.9180949},
  researchr = {https://researchr.org/publication/ChenLB20-1},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-3320-1},
}