iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS

Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi. iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. In 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018. pages 170-173, IEEE, 2018. [doi]

@inproceedings{ChenLPDS18,
  title = {iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS},
  author = {Chixiao Chen and Xindi Liu and Huwan Peng and Hongwei Ding and C.-J. Richard Shi},
  year = {2018},
  doi = {10.1109/ESSCIRC.2018.8494327},
  url = {https://doi.org/10.1109/ESSCIRC.2018.8494327},
  researchr = {https://researchr.org/publication/ChenLPDS18},
  cites = {0},
  citedby = {0},
  pages = {170-173},
  booktitle = {44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-5404-0},
}