Yuan-Ho Chen, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou. A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique. Journal of Circuits, Systems, and Computers, 23(5), 2014. [doi]
@article{ChenLSLO14,
title = {A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique},
author = {Yuan-Ho Chen and Chih-Wen Lu and Shian-Shing Shyu and Chung-Lin Lee and Ting-Chia Ou},
year = {2014},
doi = {10.1142/S0218126614500741},
url = {http://dx.doi.org/10.1142/S0218126614500741},
researchr = {https://researchr.org/publication/ChenLSLO14},
cites = {0},
citedby = {0},
journal = {Journal of Circuits, Systems, and Computers},
volume = {23},
number = {5},
}