A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique

Yuan-Ho Chen, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou. A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique. Journal of Circuits, Systems, and Computers, 23(5), 2014. [doi]

Abstract

Abstract is missing.