A Low Power 10-Bit Time-to-Digital Converter Utilizing Vernier Delay Lines

Wei Chen, Christos Papavassiliou. A Low Power 10-Bit Time-to-Digital Converter Utilizing Vernier Delay Lines. In David Al-Dabass, Alessandra Orsoni, Jasmy Yunus, Richard Cant, Zuwairie Ibrahim, editors, 15th International Conference on Computer Modelling and Simulation, UKSim 2013, Cambridge, United Kingdom, April 10-12, 2013. pages 774-779, IEEE, 2013. [doi]

Abstract

Abstract is missing.