Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors - researchr publication authors

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Yiran Chen, Kaushik Roy, Cheng-Kok Koh. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In Ingrid Verbauwhede, Hyung Roh, editors, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. pages 229-234, ACM, 2003. [doi]

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