Yiran Chen, Kaushik Roy, Cheng-Kok Koh. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In Ingrid Verbauwhede, Hyung Roh, editors, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. pages 229-234, ACM, 2003. [doi]
@inproceedings{ChenRK03,
title = {Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors},
author = {Yiran Chen and Kaushik Roy and Cheng-Kok Koh},
year = {2003},
doi = {10.1145/871506.871563},
url = {http://doi.acm.org/10.1145/871506.871563},
tags = {architecture, systematic-approach},
researchr = {https://researchr.org/publication/ChenRK03},
cites = {0},
citedby = {0},
pages = {229-234},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003},
editor = {Ingrid Verbauwhede and Hyung Roh},
publisher = {ACM},
isbn = {1-58113-682-X},
}