Wayne Chen, Lesley Shannon. An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs. In Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha, editors, 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. pages 361-364, IEEE, 2008. [doi]
@inproceedings{ChenS08-7, title = {An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs}, author = {Wayne Chen and Lesley Shannon}, year = {2008}, doi = {10.1109/FPT.2008.4762418}, url = {http://dx.doi.org/10.1109/FPT.2008.4762418}, researchr = {https://researchr.org/publication/ChenS08-7}, cites = {0}, citedby = {0}, pages = {361-364}, booktitle = {2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008}, editor = {Tarek A. El-Ghazawi and Yao-Wen Chang and Juinn-Dar Huang and Proshanta Saha}, publisher = {IEEE}, isbn = {978-1-4244-2796-3}, }