Zhi-Wei Chen, Jin-Tai Yan. Routability-constrained multi-bit flip-flop construction for clock power reduction. Integration, 46(3):290-300, 2013. [doi]
@article{ChenY13-2,
title = {Routability-constrained multi-bit flip-flop construction for clock power reduction},
author = {Zhi-Wei Chen and Jin-Tai Yan},
year = {2013},
doi = {10.1016/j.vlsi.2012.03.002},
url = {http://dx.doi.org/10.1016/j.vlsi.2012.03.002},
researchr = {https://researchr.org/publication/ChenY13-2},
cites = {0},
citedby = {0},
journal = {Integration},
volume = {46},
number = {3},
pages = {290-300},
}