Zhengbo Chen, Qi Yu, Fang Zheng, Feng Guo, Zuoning Chen. DSSA: Dual-Side Sparse Systolic Array Architecture for Accelerating Convolutional Neural Network Training. In Proceedings of the 51st International Conference on Parallel Processing, ICPP 2022, Bordeaux, France, 29 August 2022 - 1 September 2022. ACM, 2022. [doi]
@inproceedings{ChenYZGC22,
title = {DSSA: Dual-Side Sparse Systolic Array Architecture for Accelerating Convolutional Neural Network Training},
author = {Zhengbo Chen and Qi Yu and Fang Zheng and Feng Guo and Zuoning Chen},
year = {2022},
doi = {10.1145/3545008.3545086},
url = {https://doi.org/10.1145/3545008.3545086},
researchr = {https://researchr.org/publication/ChenYZGC22},
cites = {0},
citedby = {0},
booktitle = {Proceedings of the 51st International Conference on Parallel Processing, ICPP 2022, Bordeaux, France, 29 August 2022 - 1 September 2022},
publisher = {ACM},
isbn = {978-1-4503-9733-9},
}