Zhengbo Chen, Qi Yu, Fang Zheng, Feng Guo, Zuoning Chen. DSSA: Dual-Side Sparse Systolic Array Architecture for Accelerating Convolutional Neural Network Training. In Proceedings of the 51st International Conference on Parallel Processing, ICPP 2022, Bordeaux, France, 29 August 2022 - 1 September 2022. ACM, 2022. [doi]
Abstract is missing.