Design and Verification of High Performance Memory Interface Based on AXI Bus

Ming Chen, Zhifeng Zhang, Haoqi Ren. Design and Verification of High Performance Memory Interface Based on AXI Bus. In 21st International Conference on Communication Technology, ICCT 2021, Tianjin, China, October 13-16, 2021. pages 695-699, IEEE, 2021. [doi]

@inproceedings{ChenZR21-1,
  title = {Design and Verification of High Performance Memory Interface Based on AXI Bus},
  author = {Ming Chen and Zhifeng Zhang and Haoqi Ren},
  year = {2021},
  doi = {10.1109/ICCT52962.2021.9658046},
  url = {https://doi.org/10.1109/ICCT52962.2021.9658046},
  researchr = {https://researchr.org/publication/ChenZR21-1},
  cites = {0},
  citedby = {0},
  pages = {695-699},
  booktitle = {21st International Conference on Communication Technology, ICCT 2021, Tianjin, China, October 13-16, 2021},
  publisher = {IEEE},
  isbn = {978-1-6654-3206-1},
}