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Kuo-Hsing Cheng, Shun-Wen Cheng. 64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Transactions, 88-C(6):1322-1331, 2005. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder DesignKuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang. iwsoc 2004: 65-68 [doi] 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor LogiKuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao. isvlsi 2004: 233-236 [doi]
The following publications are possibly variants of this publication: