Kuo-Hsing Cheng, Shun-Wen Cheng. Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng., 22(4):975-989, 2006. [doi]
@article{ChengC06:9,
title = {Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications},
author = {Kuo-Hsing Cheng and Shun-Wen Cheng},
year = {2006},
url = {http://www.iis.sinica.edu.tw/page/jise/2006/200607_16.html},
researchr = {https://researchr.org/publication/ChengC06%3A9},
cites = {0},
citedby = {0},
journal = {J. Inf. Sci. Eng.},
volume = {22},
number = {4},
pages = {975-989},
}