Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications

Kuo-Hsing Cheng, Shun-Wen Cheng. Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng., 22(4):975-989, 2006. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.