64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design - researchr publication authors

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Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang. 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. In Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 04), 19-21 July 2004, Banff, Alberta, Canada. pages 65-68, IEEE Computer Society, 2004. [doi]

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