64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design

Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang. 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. In Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 04), 19-21 July 2004, Banff, Alberta, Canada. pages 65-68, IEEE Computer Society, 2004. [doi]

@inproceedings{ChengCH04,
  title = {64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design},
  author = {Kuo-Hsing Cheng and Shun-Wen Cheng and Chan-Wei Huang},
  year = {2004},
  doi = {10.1109/IWSOC.2004.1319851},
  url = {http://dx.doi.org/10.1109/IWSOC.2004.1319851},
  tags = {context-aware, design},
  researchr = {https://researchr.org/publication/ChengCH04},
  cites = {0},
  citedby = {0},
  pages = {65-68},
  booktitle = {Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 04), 19-21 July 2004, Banff, Alberta, Canada},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2182-7},
}