Memory Latency Reduction via Thread Throttling

Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang. Memory Latency Reduction via Thread Throttling. In 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA. pages 53-64, IEEE, 2010. [doi]

Authors

Hsiang-Yun Cheng

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Chung-Hsiang Lin

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Jian Li

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Chia-Lin Yang

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