Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment - researchr publication authors

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Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu. Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 186-187, IEEE, 2012. [doi]

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