Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie 0001, Yu Wang 0002, Huazhong Yang. TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(5):834-847, 2019. [doi]
@article{ChengXZCXWY19,
title = {TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks},
author = {Ming Cheng and Lixue Xia and Zhenhua Zhu and Yi Cai and Yuan Xie 0001 and Yu Wang 0002 and Huazhong Yang},
year = {2019},
doi = {10.1109/TCAD.2018.2824304},
url = {https://doi.org/10.1109/TCAD.2018.2824304},
researchr = {https://researchr.org/publication/ChengXZCXWY19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {38},
number = {5},
pages = {834-847},
}