Gate-level modeling for CMOS circuit simulation with ultimate FinFETs - researchr publication authors

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Nicolas Chevillon, Morgan Madec, Christophe Lallement. Gate-level modeling for CMOS circuit simulation with ultimate FinFETs. In Csaba Andras Moritz, editor, Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012. pages 22-29, ACM, 2012. [doi]

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