SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures

Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha. SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018. ACM, 2018. [doi]

@inproceedings{ChittamuruTBP18,
  title = {SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures},
  author = {Sai Vineel Reddy Chittamuru and Ishan G. Thakkar and Varun Bhat and Sudeep Pasricha},
  year = {2018},
  doi = {10.1145/3195970.3196118},
  url = {http://doi.acm.org/10.1145/3195970.3196118},
  researchr = {https://researchr.org/publication/ChittamuruTBP18},
  cites = {0},
  citedby = {0},
  booktitle = {Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018},
  publisher = {ACM},
}