40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist - researchr publication authors

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Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang. 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. on Circuits and Systems, 61-I(9):2578-2585, 2014. [doi]

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