Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang. 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. on Circuits and Systems, 61-I(9):2578-2585, 2014. [doi]
@article{ChiuHTZCJC14,
title = {40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist},
author = {Yi-Wei Chiu and Yu-Hao Hu and Ming-Hsien Tu and Jun-Kai Zhao and Yuan-Hua Chu and Shyh-Jye Jou and Ching-Te Chuang},
year = {2014},
doi = {10.1109/TCSI.2014.2332267},
url = {http://dx.doi.org/10.1109/TCSI.2014.2332267},
researchr = {https://researchr.org/publication/ChiuHTZCJC14},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {61-I},
number = {9},
pages = {2578-2585},
}