PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA - researchr publication authors

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Sung-gun Cho, Wei Tang 0010, Chester Liu, Zhengya Zhang. PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. In 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021. pages 1-2, IEEE, 2021. [doi]

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