Sung-gun Cho, Wei Tang 0010, Chester Liu, Zhengya Zhang. PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. In 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021. pages 1-2, IEEE, 2021. [doi]
@inproceedings{Cho0LZ21,
title = {PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA},
author = {Sung-gun Cho and Wei Tang 0010 and Chester Liu and Zhengya Zhang},
year = {2021},
doi = {10.23919/VLSICircuits52068.2021.9492517},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492517},
researchr = {https://researchr.org/publication/Cho0LZ21},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021},
publisher = {IEEE},
isbn = {978-4-86348-780-2},
}