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Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon. A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. on Circuits and Systems, 57-II(7):502-506, 2010. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applicationsYoung-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon. mj, 42(12):1335-1342, 2011. [doi]
The following publications are possibly variants of this publication: