HA:::2:::TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI - researchr publication related

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Kyu-won Choi, Abhijit Chatterjee. HA:::2:::TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. In Vivek De, Mary Jane Irwin, Ingrid Verbauwhede, Christian Piguet, editors, Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002. pages 207-212, ACM, 2002. [doi]

The following publications are possibly variants of this publication:

PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSIKyu-won Choi, Abhijit Chatterjee. patmos 2002: 178-187 [doi]

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