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A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs

Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula. A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. In Ayal Zaks, Bilha Mendelson, Lawrence Rauchwerger, Wen-mei W. Hwu, editors, Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016. pages 327-338, ACM, 2016. [doi]

Authors

Nitin Chugh

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Vinay Vasista

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Suresh Purini

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Uday Bondhugula

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