Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula. A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. In Ayal Zaks, Bilha Mendelson, Lawrence Rauchwerger, Wen-mei W. Hwu, editors, Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016. pages 327-338, ACM, 2016. [doi]
@inproceedings{ChughVPB16,
title = {A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs},
author = {Nitin Chugh and Vinay Vasista and Suresh Purini and Uday Bondhugula},
year = {2016},
doi = {10.1145/2967938.2967969},
url = {http://doi.acm.org/10.1145/2967938.2967969},
researchr = {https://researchr.org/publication/ChughVPB16},
cites = {0},
citedby = {0},
pages = {327-338},
booktitle = {Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016},
editor = {Ayal Zaks and Bilha Mendelson and Lawrence Rauchwerger and Wen-mei W. Hwu},
publisher = {ACM},
isbn = {978-1-4503-4121-9},
}