Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

B. Chung, J. B. Kuo. Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

This author has not been identified. Look up 'B. Chung' in GoogleThis author has not been identified. Look up 'J. B. Kuo' in Google

runs on WebDSL