B. Chung, J. B. Kuo. Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]
@inproceedings{ChungK06:3,
title = {Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology},
author = {B. Chung and J. B. Kuo},
year = {2006},
doi = {10.1109/ISCAS.2006.1693418},
url = {http://dx.doi.org/10.1109/ISCAS.2006.1693418},
tags = {optimization},
researchr = {https://researchr.org/publication/ChungK06%3A3},
cites = {0},
citedby = {0},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
publisher = {IEEE},
}