Sang-Hye Chung, Lee-Sup Kim. 1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 144-145, IEEE, 2012. [doi]
@inproceedings{ChungK12-3,
title = {1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS},
author = {Sang-Hye Chung and Lee-Sup Kim},
year = {2012},
doi = {10.1109/VLSIC.2012.6243831},
url = {http://dx.doi.org/10.1109/VLSIC.2012.6243831},
researchr = {https://researchr.org/publication/ChungK12-3},
cites = {0},
citedby = {0},
pages = {144-145},
booktitle = {Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0848-9},
}