A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS

Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng. A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS. In 2019 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, Bangkok, Thailand, November 11-14, 2019. pages 5-8, IEEE, 2019. [doi]

@inproceedings{ChungTZ19,
  title = {A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS},
  author = {Yung-Hui Chung and Chia-Hui Tien and Qi-Feng Zeng},
  year = {2019},
  doi = {10.1109/APCCAS47518.2019.8953163},
  url = {https://doi.org/10.1109/APCCAS47518.2019.8953163},
  researchr = {https://researchr.org/publication/ChungTZ19},
  cites = {0},
  citedby = {0},
  pages = {5-8},
  booktitle = {2019 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, Bangkok, Thailand, November 11-14, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-2940-2},
}