Maciej J. Ciesielski, E. Kinnen. Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems, 6(1):55-66, 1987. [doi]
@article{CiesielskiK87,
title = {Digraph Relaxation for 2-Dimensional Placement of IC Blocks},
author = {Maciej J. Ciesielski and E. Kinnen},
year = {1987},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28439&arnumber=1270246&count=17&index=6},
tags = {e-science},
researchr = {https://researchr.org/publication/CiesielskiK87},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {6},
number = {1},
pages = {55-66},
}